For each dimension, we trace: the number → the mechanism → what it changes concretely → when it does not matter.
The number: Mitsubishi FX5U basic instruction ~34 ns; Siemens S7-1200 (1214C) bit logic ~85 ns (standard).
Mechanism: That 34 ns is measured from internal register to register, hitting zero memory wait states. But in any real program — say, 10,000 lines of ladder with I/O mapping, timers, and data moves — the CPU must repeatedly fetch operands from work memory (Siemens PLC: 100 KB integrated; Mitsubishi PLC: up to 64k steps, equivalent to ~200–300 KB, but with a single-bank memory bus). Memory access latency is typically 2–5× the instruction cycle. The S7-1200’s internal memory bus uses a 32-bit wide SRAM with zero-wait-state bursts for sequential instructions, which narrows the gap to about 1.3× per instruction rather than 2.5×.
Worked consequence: For a 10,000-step program with 70% memory accesses, the effective per-instruction time becomes: Mitsubishi ~34 + (0.7 × ~110 ns) = ~111 ns/step; Siemens ~85 + (0.7 × ~25 ns) = ~103 ns/step. (illustrative, memory latency assumed from typical SRAM timing) Net result: the FX5U’s raw speed advantage evaporates under memory-bound code. The S7-1200 actually finishes a 10k-step scan in ~1.03 ms versus ~1.11 ms — about 7% faster in this regime.
When this reverses: If your program is 90% bit logic with very few memory-heavy operations (e.g., a simple state machine with
The number: S7-1200 1214C: 14 DI / 10 DO / 2 AI on-board, PROFINET interface; FX5U: up to 96 I/O on CPU (512 with CC-Link), built-in Ethernet + RS-485.
Mechanism: Neither datasheet publishes I/O update time per point. However, the bus architecture differs: Siemens uses a dedicated PROFINET ASIC with hardware DMA for I/O image updates, which can update 24 digital I/O in about 15–20 µs (derived from typical PROFINET cycle times). Mitsubishi’s FX5U updates I/O via a CPU-driven bus that also manages analog, high-speed counters, and positioning; a single analog read (12-bit) can take 80–120 µs. If your loop reads 2 analog channels (e.g., pressure + flow), that’s ~200 µs per scan that the S7-1200 avoids because its analog read is integrated into the same bus cycle at essentially no extra latency (the 2 AI are sampled on-board and appear in the I/O image).
Worked consequence: In a closed-loop PID application scanning 2 analogs and 12 digital inputs, the S7-1200’s total I/O update time is ~25 µs; the FX5U’s is ~220 µs. At a 10 ms target cycle, the FX5U spends 2.2% vs 0.25% on I/O — that’s 8.8× overhead. For any loop requiring
When this reverses: If your application uses zero analog inputs and fewer than 16 digital I/O, the FX5U’s overhead drops to ~15 µs (comparable to Siemens). Also, if you use CC-Link remote I/O (512 points), the bus master handles the load, but scan time increases linearly with remote nodes — not unique to either brand.
The number: S7-1200 programmed in TIA Portal (IEC 61131-3); FX5U programmed in GX Works3 (IEC 61131-3). Both compile to native code. But TIA Portal’s runtime environment includes an implicit OS scheduler that can add 30–50 µs per scan for background tasks (diagnostics, web server, PROFINET IO supervision). GX Works3’s runtime is leaner — it does not run a separate OS; the firmware directly executes the compiled step sequence.
Mechanism: The S7-1200’s “scan” includes a prologue (I/O image copy, 8–12 µs), user program execution, then epilogue (I/O image write, alarm handling). The FX5U’s scan is more linear: I/O copy is done during the same bus cycle as program execution, saving about 10 µs per scan. This is a fixed overhead — for a 1 ms scan, it’s 1%; for a 100 µs scan, it’s 10%.
Worked consequence: For a high-speed application (e.g., a packaging machine with 500 µs target cycle), the S7-1200’s fixed overhead of ~50 µs consumes 10% of the budget, leaving 450 µs for user code. The FX5U’s overhead ~20 µs consumes 4%, leaving 480 µs — a 6.7% advantage. Over a 10-hour shift, the FX5U can process about 3.6 million more scans.
When this reverses: If your cycle time is >10 ms (most process control, HVAC, water treatment), the overhead difference is negligible (
| Rank | PLC | Best For | Key Runtime Tipping Point |
|---|---|---|---|
| 1 | Siemens S7-1200 (1214C) | Mixed I/O, analog-heavy, networked applications with cycle times >2 ms | Superior memory bus efficiency and PROFINET DMA make real-world scan competitive even with slower instruction spec; I/O overhead ~10× lower than FX5U when ≥2 analogs used |
| 2 | Mitsubishi FX5U | Pure digital, high-speed bit logic, very short cycle times ( | Faster instruction speed and lean runtime give ~7% advantage in sub-500 µs loops; but overhead penalty becomes severe with analog I/O |
effective_cycle = 3 × basic_instruction_time × steps + I/O_overhead. If that exceeds your target, step up to a larger controller.
Topology/standards per the cited standards; all product ratings are manufacturer-stated values from the cited datasheets, current to 2026-06; derived/illustrative figures are labelled as such. This is not an independent head-to-head test. Siemens is a brand affiliated with this site; competitor names are used for identification only.